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2.3GHz to 2.7GHz MIMO Wireless
BroadbandRF Transceiver
Table 17. Register 14: HPFSM 3 Register (Address = 01110, Default = 3C5 HEX )
BIT NAME
TXGATE_EN
RESERVED
HPC_STOP_M2<1:0>
HPC_STOP<1:0>
HPC_DELAY<1:0>
HPC_1k_GAIN<1:0>
BIT LOCATION
(0 = LSB)
9
8
7:6
5:4
3:2
1:0
DESCRIPTION
PA driver and DAC on/off state gated by PLL lock detect.
0 = Independent of PLL lock detect
1 = Disable PA driver when PLL lock detect = 0 (default)
Reserved bits—set to default
Rx VGA on-hold highpass corner when RXHP = 1. Test at settings 00, 01, and
11. Only active when Reg15_D9 = 1.
00 = 1kHz
01 = 30kHz
10 = 100kHz
11 = 600kHz (default)
Rx VGA final highpass corner selection. Test at settings 00, 01, and 11.
00 = 100Hz (default)
01 = 1kHz
10 = 30kHz
11 = 100kHz
Rx VGA HPC A and HPC D rising edge delay for 100k, 30k, 1k, and 100Hz
highpass corner. Test at settings 00, 01, and 11.
00 = 0μs
01 = 0.2μs (default)
10 = 0.4μs
11 = 0.6μs
Rx VGA highpass corner duration at 1kHz. Triggered by LNA gain change.
Test at settings 00, 01, and 10.
00 = 0μs
01 = 3.2μs (default)
10 = 6.4μs
11 = 9.6μs
Table 18. Register 15: HPFSM 4 Register (Address = 01111, Default = 201 HEX )
BIT NAME
HP_MODE
RESERVED
HPC_SEQ_BYP
RESERVED
BIT LOCATION
(0 = LSB)
9
8:7
6
5:0
DESCRIPTION
Highpass corner control using RXHP.
0 = Highpass corner switches automatically without RXHP
1 = Highpass corner switches dependent on RXHP (default)
Reserved bits—set to default
Highpass corner switching sequence bypassed during RXHP transition from
1 to 0.
0 = Start switching from highpass corner set by HPC_STOP_M2<1:0> in
register 14 and continue with programmed sequence (default)
1 = Switch from highpass corner set by HPC_STOP_M2<1:0> directly to
final highpass corner set by HPC_STOP<1:0> in register 14.
Reserved bits—set to default
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31
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